The discussion about the next generation of DDR memory (DDR5) has been a breakthrough in recent months, as manufacturers have shown a wide variety of test vehicles before a full release of the product. Platforms planning to use DDR5 are also fast approaching, with an expected debut on the business side before slowly losing out to the consumer. As with all these things, development takes place in stages: memory controllers, interfaces, ip-equivalent electrical test and modules. It’s that final stage that SK Hynix is launching recently, or at least the chips that come into these modules. DDR5 is the next stage of platform DRAM memory to be used on most major computing platforms. The specification reduces the main voltage from 1.2 V to 1.1 V, increases the maximum density of the silicon mold by a factor of 4, doubles the maximum data speed, doubles the burst length and doubles the number of banking groups. Simply put, JEDEC’s DDR specification allows for a 128GB unbuffered module running on DDR5-6400. RdimMs and LRDIMM should be able to go much higher, if power allows.
There are four corners in the DDR world that everyone involved in the specification wants to iterate through. Capacity is obvious, but memory bandwidth also plays a key role in scaling the performance of common multicore workloads on the high-core servers we’re looking at. The other two are power (an obvious goal) and the other is latency, another key metric for performance.
With DDR5 memory, one of the main changes to help drive this is the way the system sees memory. Instead of being a single 64-bit data channel per module, DDR5 looks like two 32-bit data channels per module (or 40 bits in ECC). The burst length is doubled, which means that each 32-bit channel will still provide 64 bytes per operation, but you can do it in a more interleaved way.
This means that the standard “64-bit DDR4 two-channel” system will be transformed into a “quad 32-bit DDR5 channel” arrangement, although each memory stick provides a total of 64 bits, but in a more controllable way. This also facilitates doubling the speed of data, a key element to increase maximum bandwidth, as well as a finer bank update feature, which allows asynchronous operations in memory during use, reducing latency.
Voltage regulation is also moving from the motherboard to the memory module, allowing the module to adjust its needs. We’ve already seen DDR4 adopt Vdroop per-chip control, but this takes the whole idea a step further for stricter power control and management. It also puts power management in the hands of the module vendor rather than the motherboard manufacturer, allowing the module manufacturer to scale what is needed for faster memory: it will be interesting to see how the different firmwares deal with the standard non-JEDEC gaming memory that will surely , exceed the specifications.
SK Hynix did not provide information on the under-timing of these modules. The JEDEC specification defines three different modes for DDR5-4800:
DDR5-4800A: 34-34-34
DDR5-4800B: 40-40-40
DDR5-4800C: 42-42-42
SK Hynix quotes that DDR5 is expected to be 10% of the global market by 2022, rising to 43% by 2024. The intersection point for consumer platforms is a bit blurry at this point, as we’re probably only halfway (or less than half) through the DDR4 cycle. Traditionally, we expect cost interception between old and new technology when they are equal in market share, however, the additional costs in regulating the voltage that ddr5 requires will likely increase module costs, scaling from standard power delivery on JEDEC modules to a more resilient solution on overclocked modules. However, it should make motherboards cheaper in that regard. Source: SK Hynix
